1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating a ferroelectric material (hereinafter referred to as a xe2x80x9cferroelectric memory devicexe2x80x9d). More specifically, the present invention relates to a ferroelectric memory device including memory elements (memory cells) each composed of at least one semiconductor transistor and at least one ferroelectric capacitor, such that at least one of the memory cells is selected based on activation of the semiconductor transistor associated therewith, and information is stored in the selected memory cell based on a polarization direction of the associated ferroelectric capacitor.
2. Description of the Related Art
FIGS. 9 and 10 show the respective memory cell structures of commonly-used ferroelectric memory devices 900 and 1000. The conventional ferroelectric memory device 900 shown in FIG. 9 is of a type referred to as xe2x80x9c2-transistor-2-capacitorxe2x80x9d (hereinafter xe2x80x9c2T2Cxe2x80x9d), in which each memory cell is composed essentially of two semiconductor transistors 1 and two ferroelectric capacitors 2. One piece of data is stored in one memory cell. The conventional ferroelectric memory device 1000 shown in FIG. 10 is of a type referred to as xe2x80x9c1-transistor-1-capacitorxe2x80x9d (hereinafter xe2x80x9c1T1Cxe2x80x9d), in which each memory cell is composed essentially of one semiconductor transistor 1 and one ferroelectric capacitor 2. One piece of data is stored in one memory cell.
In the conventional ferroelectric memory device 900 shown in FIG. 9, word lines (WL0, WL1) and bit lines (BIT0, BIT0#, BIT1, BIT1#, BIT2, BIT2#, BIT3, BIT3#, etc.) intersect each other (illustrated as perpendicularly intersecting each other in FIG. 9), and the word lines and plate lines (PL0, PL1) are disposed in parallel to each other. A source of each semiconductor transistor 1 is coupled to one of the bit lines; a drain of each semiconductor transistor 1 is coupled to a first electrode of the associated ferroelectric capacitor 2; a gate of each semiconductor transistor 1 is coupled to one of the word lines; and a second electrode of the associated ferroelectric capacitor 2 is coupled to one of the plate lines. Furthermore, a pair of bit lines (BIT0 and BIT0#; BIT1 and BIT1#; BIT2 and BIT2#; BIT3 and BIT3#, etc.) are coupled in common to a sense amplifier 3.
In the ferroelectric memory device 900 of FIG. 9, each semiconductor transistor 1 and its associated ferroelectric capacitor 2 are provided in the vicinity of an intersection between a bit line and a word line. On the other hand, in the ferroelectric memory device 1000 of FIG. 10, each semiconductor transistor 1 and its associated ferroelectric capacitor 2 are provided in the vicinity of an intersection between every other bit line and a word line (e.g., an intersection between the bit lines BIT0 and BIT0# and the word line WL0).
In the ferroelectric memory devices 900 and 1000, a memory cell may be selected in the following manner. First, the word line WL0 may be selected so as to go high (xe2x80x9cHxe2x80x9d), and then a pulse voltage may be applied to the plate line PL0. (Similarly, the word line WL1 may be selected so as to go high (xe2x80x9cHxe2x80x9d), and then a pulse voltage may be applied to the plate line PP1). The applied pulse voltage, if applied in the same direction as the polarization direction of each ferroelectric capacitor 2, destroys the polarization of that ferroelectric capacitor 2 so that its polarization direction is inverted. As a result, those memory cells in which the polarization of the ferroelectric capacitors 2 is inverted output a different charge amount on the associated bit line from the charge amount output by those memory cells in which the polarization of the ferroelectric capacitors 2 is not inverted. Specifically, those memory cells in which the polarization of the ferroelectric capacitors 2 is inverted output a higher charge amount from their respective ferroelectric capacitors 2 than those memory cells in which the polarization of the ferroelectric capacitors 2 is not inverted. These differential charge amounts are amplified by the sense amplifiers 3, resulting in xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d data being output on the corresponding bit lines.
However, in accordance with the structures of FIGS. 9 and 10, a large number of ferroelectric capacitors 2 are directly coupled to each plate line. Since the ferroelectric capacitors 2 have a relatively large capacitance, delays on the plate line become more problematic as more ferroelectric capacitors 2 are coupled to the plate line. In general, a ferroelectric capacitor has a capacitance which is about 10 times or more of the gate capacitance of a semiconductor transistor. Therefore, if the number of semiconductor transistors coupled to a word line is the same as the number of ferroelectric capacitors coupled to a plate line, then the plate line has a capacitance which is about 10 times or more of that of the word line.
In order to solve this problem, Japanese Laid-Open Publication No. 10-162589 proposes a xe2x80x9c2T2Cxe2x80x9d type ferroelectric memory device 1100 structure as shown in FIG. 11. The ferroelectric memory device 1100 includes a plurality of plate lines corresponding to each word line (so that plate lines PL0A and PL0B correspond to a word line WL0; plate lines PL1A and PL1B correspond to a word line WL1). For example, the plate lines PL0A and PL0B correspond to the word line WL0. The plate line PL0A corresponds to bit lines BIT0, BIT0#, BIT1 and BIT1#. The plate line PL0B corresponds to bit lines BIT2, BIT2#, BIT3 and BIT3#. Otherwise, the ferroelectric memory device 1100 has the same structure as that of the ferroelectric memory device 900 of FIG. 9. Since the structure of the ferroelectric memory device 1100 reduces the number of ferroelectric capacitors coupled to the plate lines to a half of what it would be otherwise, the operational speed of the plate lines is improved.
Although not disclosed in the 10-162589 application, an application of this technique to a xe2x80x9c1T1Cxe2x80x9d type configuration should be as shown in FIG. 12. Specifically, plate lines PL0A and PL0B are provided so as to correspond to a word line WL0, and plate lines PL1A and PL1B are provided so as to correspond to a word line WL1. The plate lines PL0A and PL1A correspond to bit lines BIT0, BIT0#, BIT1 and BIT1#. The plate lines PL0B and PL1B correspond to bit lines BIT2, BIT2#, BIT3 and BIT3#. Otherwise, the ferroelectric memory device 1200 has the same structure as that of the ferroelectric memory device 1000 of FIG. 10.
However, in accordance with the ferroelectric memory device 1100 (or 1200) shown in FIG. 11 (or 12) of the 10-162589 application, a word line is selected based on a ROW address, and a plate line is selected based on a COL address. According to this method, the sense amplifiers cannot operate before it is determined which one of the plate lines is to be activated. Under a DRAM type input (i.e., address multiplex) scheme, this results in an increased access time. Since a period of time must be waited in order for a COL address to be input, this structure cannot provide for an enhanced operational speed, in spite of the reduction of the plate line capacitance (which would otherwise enable some enhancement in the operational speed).
Furthermore, there is also a problem in that adjoining bit lines are simultaneously sensed in all of the ferroelectric memory devices 900, 1000, 1100, and 1200 shown in FIGS. 9, 10, 11 and 12, thereby resulting in a reduced sensing margin (since the sensing of one bit line may always be influenced by, or subjected to the interference of, an adjoining bit line).
A ferroelectric memory device including: a matrix of memory cells each including a semiconductor transistor and a ferroelectric capacitor; a plurality of word lines and a plurality of bit lines provided so as to intersect each other; and a plurality of plate lines provided substantially in parallel to the word lines, at least two plate lines corresponding to each of the word lines, wherein a drain of the semiconductor transistor is coupled to a first electrode of the ferroelectric capacitor; a source of the semiconductor transistor is coupled to a corresponding one of the plurality of bit lines; a gate of the semiconductor transistor is coupled to a corresponding one of the plurality of word lines; and a second electrode of the ferroelectric capacitor is coupled to a corresponding one of the plurality of plate lines, the ferroelectric memory device further including: a selection/driving circuit being coupled to the plurality of word lines and the plurality of plate lines and receiving a ROW address, the ROW address being divided into a first portion and a second portion, wherein the first portion of the ROW address is used to select and activate at least one of the plurality of word lines, the at least one word line defining a broader area than is designated by the ROW address, and wherein the second portion of the ROW address is used to select and activate at least one of the plurality of plate lines, thereby selecting at least one of the plurality of memory cells whose corresponding word line and whose corresponding plate line are both activated.
In one embodiment of the invention, two or more plate lines are provided so as to correspond to each of the plurality of word lines, and memory cells coupled to adjoining ones of the plurality of bit lines are coupled to different ones of the plurality of plate lines.
In another embodiment of the invention, the ferroelectric memory device further includes a transfer gate for electrically coupling a selected one of the plurality of bit lines to a sense amplifier and a grounding transistor for electrically isolating an unselected one of the plurality of bit lines from a sense amplifier, wherein a signal for controlling the transfer gate fixes the unselected one of the plurality of bit lines at a level which will not destroy data stored in the unselected memory cells.
In still another embodiment of the invention, the ferroelectric memory device further includes sense amplifiers coupled to the plurality of bit lines, wherein a signal for activating at least one of the sense amplifiers that is coupled to the selected one of the plurality of bit lines fixes the unselected one of the plurality of bit lines at a level which will not destroy data stored in the unselected memory cells.
In still another embodiment of the invention, the selection/driving circuit selects two or more of the plurality of memory cells coupled to the same one of the plurality of bit lines by selecting and activating two or more of the plurality of word lines, and wherein the selection/driving circuit further selects at least one memory cell from among the two or more selected memory cells coupled to the same bit line by selecting and activating at least one of the plurality of plate lines.
Alternatively, a ferroelectric memory device according to the present invention includes: a matrix of memory cells each including a semiconductor transistor and a ferroelectric capacitor; a plurality of word lines and a plurality of bit lines provided so as to intersect each other; and a plurality of plate lines provided substantially in parallel to the word lines, at least two plate lines corresponding to each of the word lines, wherein a drain of the semiconductor transistor is coupled to a first electrode of the ferroelectric capacitor; a source of the semiconductor transistor is coupled to a corresponding one of the plurality of bit lines; a gate of the semiconductor transistor is coupled to a corresponding one of the plurality of word lines; and a second electrode of the ferroelectric capacitor is coupled to a corresponding one of the plurality of plate lines, and wherein memory cells coupled to adjoining ones of the plurality of bit lines are coupled to different ones of the plurality of plate lines.
In one embodiment of the invention, the ferroelectric memory device further includes a transfer gate for electrically coupling a selected one of the plurality of bit lines to a sense amplifier and a grounding transistor for electrically isolating an unselected one of the plurality of bit lines from a sense amplifier, wherein a signal for controlling the transfer gate fixes the unselected one of the plurality of bit lines at a level which will not destroy data stored in the unselected memory cells.
In another embodiment of the invention, the memory device further includes sense amplifiers coupled to the plurality of bit lines, wherein a signal for activating at least one of the sense amplifiers that is coupled to the selected one of the plurality of bit lines fixes the unselected one of the plurality of bit lines at a level which will not destroy data stored in the unselected memory cells.
In still another embodiment of the invention, the selection/driving circuit selects two or more of the plurality of memory cells coupled to the same one of the plurality of bit lines by selecting and activating two or more of the plurality of word lines, and wherein the selection/driving circuit further selects at least one memory cell from among the two or more selected memory cells coupled to the same bit line by selecting and activating at least one of the plurality of plate lines.
Thus, the invention described herein makes possible the advantages of (1) providing a ferroelectric memory device which can provide for an enhanced operational speed based on the reduction of the plate line capacitance without employing COL addresses; and (2) providing a ferroelectric memory device which can provide for an improved sensing margin by preventing interference from adjoining bit lines.